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16-bit precision, low power meter on a chip with cortex-m3 and connectivity data sheet ADUCM350 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014 analog devices, inc. all rights reserved. technical support www.analog.com features analog performance 160 ksps, 16-bit, precision analog-to-digital converter (adc) 4 dedicated voltage measurement channels 8 current measurement channels impedance measurement engine high precision voltage reference supply noise rejection filtering ultralow leakage configurable switch matrix 12-bit digital-to-analog converter (dac) precision instrumentation amplifier control loop 6-channel captouch controller temperature sensor analog hardware accelerators autonomous analog front-end (afe) controller independent sequencer for afe functions direct digital synthesizer (dds)/arbitrary waveform generator receive filters complex impedance measurement (dft) engine processing 16 mhz arm cortex-m3 processor 384 kb of embedded flash memory 32 kb system sram 16 kb flash configured eeprom integrated full-speed usb 2.0 controller and phy multilayer advanced microcontroller bus architecture (amba) bus matrix central direct memory access (dma) controller real-time clock (rtc) general-purpose, wake-up, and watchdog timers communication input/output i 2 s and beeper interface lcd display controller (parallel and serial) lcd segment controller spi, i 2 c, and uart peripheral interfaces programmable gpios power coin cell battery compatible 2.5 v to 3.6 v active measurement range power management unit (pmu) power-on reset (por) and power supply monitor (psm) packages and temperature range operating temperature range: ?40c to +85c package: 120-lead, 8 mm 8 mm csp_bga applications point-of-care diagnostics body-worn devices for monitoring vital signs amperometric, voltametric, and impedometric measurements functional block diagram figure 1. ahb \ apb bridge lcd tmr0 tmr1 wdt crc pmu misc beep abp \ 1 tmr2 rtc gpio uart spi0 spi1 i 2 c abp \ 0 i 2 s 1 256kb 1 128kb flash 16kb eeprom sram1 (16kb) pdi pll lf xtal hf osc lf osc hf xtal por psm hp ldo captouch lp ldo spih amba bus matrix usb dma nvic trace sw/jtag arm cortex-m3 sram0 (16kb) afe controller dft signal generation afe 16-bit precision adc precision reference switch matrix 12-bit dac in-amp control loop tia receive filters usb phy 12073-001
ADUCM350* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ADUCM350 evaluation board documentation application notes ? an-1262: ADUCM350 serial download protocol ? an-1263: security integrity of the ADUCM350 ? an-1271: optimizing the ADUCM350 for impedance conversion ? an-1281: amperometric/potentiostat measurements using the ADUCM350 ? an-1282: profiling the ADUCM350 supply current in an example application ? an-1286: ADUCM350 analog front end accuracy in a noisy digital environment ? an-1293: a quick guide to the ADUCM350 sequencer ? an-1302: optimizing the ADUCM350 for 4-wire, bio- isolated impedance measurement applications data sheet ? ADUCM350: 16-bit precision, low power meter on a chip with cortex-m3 and connectivity data sheet user guides ? ug-587: ADUCM350 hardware reference manual ? ug-668: eval-ADUCM350ebz user guide ? ug-677: ADUCM350 software development kit quick start guide reference materials technical articles ? home is where the heart is design resources ? ADUCM350 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ADUCM350 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ADUCM350 data shee t rev. a | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 analog front - end specifications ............................................... 4 switch matrix specifications ....................................................... 5 transimpedance amplifier specifications ................................ 6 adc specifications ...................................................................... 6 temperatur e sensor specifications ............................................ 6 captouch ....................................................................................... 6 dft - based impedance measurements ..................................... 7 digital platform ............................................................................ 7 system clocks/timers ............................................................... 10 power management specifications .......................................... 12 trickle charger ........................................................................... 12 timing characteristics .............................................................. 13 absolute maximum ratings .......................................................... 19 thermal resistance .................................................................... 19 esd caution ................................................................................ 19 pin configuration and function descriptions ........................... 20 typical performance characteristics ........................................... 25 analog front end ........................................................................... 30 excitation stage .......................................................................... 30 measurement stage .................................................................... 32 afe contro l ................................................................................ 33 captouch features ..................................................................... 33 microsubsystem ............................................................................. 34 memories ..................................................................................... 34 debug capability ........................................................................ 34 programmable gpios ............................................................... 34 timers .......................................................................................... 34 usb ............................................................................................... 34 power management and clo cking ........................................... 35 display options .......................................................................... 35 audio options ............................................................................ 36 development support .................................................................... 37 documentation ........................................................................... 37 hardware ..................................................................................... 37 software ....................................................................................... 37 packaging and ordering information ......................................... 38 outline dimensions ................................................................... 38 ordering guide .......................................................................... 38 revision history 5/ 14 rev ision a : initial version
data sheet ADUCM350 rev. a | page 3 of 40 general description the ADUCM350 is a complete, coin cell powered, high precision, meter - on - chip for portable device applications for applications such as point - of - care diagnostics and body - worn devices for monitoring vital signs . the ADUCM350 is designed for high precision amperom e t ric, voltametric, and impedometric measurement capabilities . the ADUCM350 analog front end ( af e ) features a 16 - bit , precision , 160 ksps analog - to - digital converter ( adc ) ; 0.17% precision voltage reference ; 12 - bit , no missing codes digital - to - analog converter ( dac ) ; and a reconfigurable ultra low leakage switch matrix. the ADUCM350 also includes a n arm ? cortex - m3 - based processor, memory, and all i/o connectivity to support portable meters with display, usb communication, and active sensors. the ADUCM350 is available in a 120 - lead , 8 mm 8 mm csp_bga and operates from ?40c to + 85c. to support extremely low dynamic and hibernate power management, the ADUCM350 provides a collection of power modes and features , such as dynamic and software controlled clock gating and power gating. the afe is connected to the arm cortex - m3 via an advanced high performance bus ( ahb ) slave interface on the advanced microcontroller bus architecture ( amba ) matrix , as well as direct memory access ( dma ) and interrupt connections.
ADUCM350 data shee t rev. a | page 4 of 40 specifications all characterization is at vccm = 2.5 v to 3.6 v, specifications below 2.5 v are for functionality only, all minimum and maxi mum specifications are specified for a temperature range of ?40c to +85c, unless otherwise noted. analog front - end specification s afe ldo specifications tale afe ldo specifications parameter min typ max unit test conditions/comments voltage output voltage 1.71 1.8 1.89 v measured with a load capacitance ( c load ) = 0.47 f; measured with 1 ma load current on avdd_rx/tx ; all afe blocks powered down dropout 150 200 mv 10 ma load applied; no afe blocks enabled regulation line 1080 v/v 10 ma load applied load 0.65 mv/ma 10 ma load applied power up power - up time 500 s measured with a c load = 0.47 f; current limit enabled high precision internal reference specifications tale 2 high precision internal reference specifications parameter min typ max unit test conditions/comments adc v ref reference voltage initial accuracy 1 1.797 1.8 1.803 v for a temperature range of 0c to 50c 1.79 1.8 1.803 v for a temperature range of ?40c to +85c output impedance 570 m ldo and reference enabled; all other afe blocks disabled; reference loaded with 50 a on vref temperature coefficient 2 ? 52 +90 ppm/c for a temperature range of ?40c to +85c , maximum value from ?40c to +25c , and from +25c to +85c specified ?45 +48 ppm/c for a temperature range of 0c to 50c , maximum value from ?40c to +25c , and from 25c to 85c specified vref thermal hysteresis 50 ppm ref_excite switching load 1.789 1.793 1.797 v i load = 200 a; internal adc measurement line regulation 50 v/v v ccm1 = 2.5 v, v ccm2 = 3.6 v; reference loaded with 300 a short - circuit current to ground 10 ma current limit off dac v ref reference voltage 1.77 1.8 1.83 v vbias vbias voltage 1.095 1.1 1.102 v measured with a c load = 0.47 f; no current load 1 reference v oltage is trimmed unloaded. measured with c load = 4.7 f. measured at 25c. 2 guaranteed by design and/or characterization.
data sheet ADUCM350 rev. a | page 5 of 40 dac/rcf/pga specifications table 3 . dac/pga /rcf specifications parameter 1 min typ max unit test conditions/comments dac output range ? 600 +600 mv as seen by sensor resolution 12 bits integral nonlinearity (inl) 0.85 lsb measured at an output of the excitation loop, using gain = 1 and default dac clock ( 16 m hz 49 dac clock speed) differential nonlinearity ( dnl ) ?1 +1 lsb measured at an output of the excitation loop, using g ain = 1 and default dac clock (16 m hz 49 dac clock speed ) full - scale error positive 0.2 % fsr pga ( g ain = 1), measured at an output of the excitation loop, dac code = 0xe00 1 % fsr pga (gain = 0.025), measured at an output of the excitation loop , dac code = 0xe00 negative 0.2 % fsr pga ( g ain = 1), measured at an output of the excitation loop, dac code = 0x200 1 % fsr pga ( g ain = 0.025), measured at an output of the excitation loop, dac code = 0x200 offset error, midscale 1 mv pga ( g ain = 1 or gain = 0.025), measured at an output of the excitation loop across rcal clocking frequency 280.7 320 380.95 khz programmable gain amplifier ( pga ) gain from pga in state 0 1 covered by dac full - scale error measured on an output of the excitation loop gain from pga in state 1 0.025 covered by dac full - scale error measured on an output of the excitation loop reconstruction filter ( rcf ) 3 db corner frequency 50 khz 1 there may be some system offsets and gain errors that can be calibrated at the system level to improve dc accuracy. hence, the voltage swing at the output of the dac is 8 00 mv to guarantee 6 00 mv swing on the sensor. switch matrix specif ications table 4. switch matrix specifications parameter min typ max unit test conditions/comments r on 1 current carrying switches d x , dr1, t x , and tr 2 40 50 ivs 40 75 noncurrent carrying switches p x , n x , and nr2 600 900 pr1 600 950 nl 260 350 pl 210 260 dc off leakage 2 t and n switches 370 pa sum value of four t switc h es and four n switches p switches 340 pa sum value of four p switches d switches 350 pa sum value of four d switches
ADUCM350 data shee t rev. a | page 6 of 40 parameter min typ max unit test conditions/comments dc o n leakage 2 t, n , and p switches 530 pa sum value for 25 s witches , including nl d switches 340 pa sum value for eight s witches 1 r on characterized with a voltage sweep from 0 v to vccm. production tested at 1.8 v. 2 see figure 38 as a reference. the afe x pin is driven to 0.2 v. trans i mpedance amplifier specifications table 5. transi mpedance amplifier specifications parameter min typ max unit test conditions/comments transimpedance amplifier maximum current sink/source 5 ma ensure an r tia selection to generate 750 mv swing fo r optimal linearity performance short - circuit protection functionality 10 ma adc specifications table 6. adc specifications 1 parameter min typ max unit test conditions/comments adc input range 0.35 1.85 v internal r eference no missing codes 16 b its dnl 0.9 lsb inl 0.7 lsb @ 160 k sps with respect to an optimal voltage range of 750 mv , f rom 0c to 50c 1 lsb @ 160 ksps with respect to an optimal voltage range of 750 mv , f rom ?40 c to +85c sample rate after decimation 160 ksps 3 db bandwidth 54 khz 1 r tia = 7.5 k , c tia = 220 pf; 100 a current measurement. temperature sensor specifications table 7. temperature sensor specifications parameter min typ max unit test conditions/comments temperature sensor accuracy 1 c 0c to 50c , t rimmed at 25 c 2 c ?40c to +85c , t rimmed at +25c c ap t ouch table 8. captouch specifications parameter min typ max unit test conditions/comments captouch ? characteristics core resolution 14 bits core snr 60 db 1 khz t est tone, input range of adc = 1.8 v capt_ x 10 na gpio leakage test update rate 7.5 1e6 s programmable, dependent on configuration update rate per sensor 7.5 s no filtering enabled, clock = 16 mhz capt_ x input range 8 pf ?c in is register programmable from 0.5 pf to 9.3 pf capt_ x offset (capdac) range 75 pf
data sheet ADUCM350 rev. a | page 7 of 40 parameter min typ max unit test conditions/comments capdac resolution 0.1 pf output nois e peak -to - peak 8 codes rms 1.3 codes dft - based impedance measuremen ts table 9. dft - based impedance measurements 1 parameter min typ max unit test conditions/comments impedance accuracy 2 magnitude 0.33 % standard d eviation as a percent of z phase 0.17 degrees standard d eviation of z precision 3 magnitude 0.17 % standard d eviation as a percent of z phase 0.08 degrees standard d eviation of z 1 for a z of 181 (0.02% tolerant resistor). excitation frequency = 20 khz , sine amplitude = 9 mv rms , r cal = 1 k, r tia = 7.5 k, c tia = 220 pf. measurements at 25 c . single dft measurement. 2 device - to - device repeatability for 1000 devices. 3 single device, repeatable measurements. digital platform digital ldo table 10. digital ldo specifications parameter min typ max unit test conditions/comments output voltage 1.71 1.8 1.89 v measured with a c load = 0.47 f, m easured with a 10 ma load current on dvdd dropout 150 200 mv 10 ma load applied , n o afe blocks enabled regulation line 1.4 mv/v 10 ma load current on dvdd load 0.41 mv/ma 0 ma to 10 ma load current power - up time 42 s time taken from ldo enable to when ldo voltage is within spec ification, c load = 0.47 f, r egulator unloaded low power ldo table 11. low power ldo specifications parameter min typ max unit test conditions/comments output voltage 1.71 1.8 1.89 v regulation line 0.45 mv/v v ccm = 2.0 v to 3.6 v load 28.5 mv/ma 0 a to 100 a l oad
ADUCM350 data shee t rev. a | page 8 of 40 f lash /g eneral - purpose flash table 12. flash/general - purpose flash specifications parameter min typ max unit test conditions/comments flash/gp flash endurance 1 20,000 cycles erase time 20 ms @ 1.8 v program time 20 s @ 1.8 v data retention 2 100 years below room temperature 1 endurance is qualified to 10,000 cycles as per jedec std. 22 method a117 and measured at ?40c, +25c, and +125c. typical endurance at 25 c is 170,000 cycles. 2 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec std. 22 method a117. retenti on lifetime derates with junction temperature. digital inputs/outputs : specified specified pin supply range from 2 to table 13. digital inputs and outputs 1 specifications parameter min typ max unit test conditions/comments pin supply 2.5 3 3.6 v impedance pull - down 20 k i sink < 10 a pull - up 15 k i sourc e < 10 a internal pull - up/pull- down enabled leakage 2 200 a digital i/o leakage current .01 1 a input capacitance 10 pf input voltage low (v inl ) 0.3 pin supply v high (v inh ) 0.7 pin supply v output voltage low (v ol ) 0.4 v i sink = 1.0 ma v ol high drive 0.4 v i sink = 1.6 ma high (v oh ) 3 pin supply ? 0.4 v i source = 1.0 ma v oh high drive 2.4 v i source = 1.6 ma 1 includes gpio, debug, spi, i 2 c, pdi, lcd, i 2 s, and beeper. 2 see table 35 for details regarding bumps/pins that have pull - up resistor s. 3 i 2 c does not drive out a high voltage; it uses external pull - up resistors. digital inputs/outputs : functional functional pin supply range from to 2 table 14. digital inputs/outputs: functional specifications parameter min typ max unit test conditions/comments pin supply 1.65 2.5 v input voltage low (v inl ) 0.3 pin supply v high (v inh ) 0.7 pin supply v output voltage low (v ol ) 0.45 v i sink = 1.0 ma high (v oh ) 1 pin supply ? 0.5 v i source = 1.0 ma 1 i 2 c does not drive out a high voltage; it uses ext ernal pull - up resistors.
data sheet ADUCM350 rev. a | page 9 of 40 universal serial bus regulator specifications table 15. universal serial bus regulator specifications parameter min typ max unit test conditions/comments serial bus regulator input voltage range 3.6 5.25 v regulated output voltage 3.2 3.4 v dropout 440 mv 40 ma continuous current regulation line 0.0043 %/v 4.5 v to 5.5 v load 0.0093 %/ma @ 5 v , 220 nf ceramic decoupling cap acitor power - up time 37 s universal serial bus dc specifications table 16. universal serial bus dc specifications parameter min typ max unit test conditions/comments receiver single - ended input voltage (driven) high 2.0 v low 0.8 v differential receiver input common mode 0.8 2.5 v sensitivity 0.2 v v( usb dp) ? v( usb dm) transmitter output voltage low (v ol ) 0 0.3 v pull - up resistor asserted on the usb pin, usb dp , r pu to avdd high (v oh ) 2.8 3.6 v pull - down resistor asserted on usb dp and usb dm (15 k to gnd) driver output impedance 28 44 r driver + r series term series resistor 40 pull -up r esistor (d+ high) 1.425 1.5 3.095 k termination v oltage = usb regulator voltage pull - up resistor (d+ low) 0.9 1.575 k termination v oltage = usb regulator voltage pull -d own r esistors 14.25 15 24.8 k universal serial bus ac specifications meeting usb 2 compliance electrical tests table 17. universal serial bus ac specifications parameter min typ max unit test conditions/comments full speed driver timing c load = 50 pf signaling rate 11.988 12 mhz output time rise 4 20 ns v oh ? v ol (10% to 90%) , c load = 50 pf fall 4 20 ns v oh ? v ol (10% to 90%) , c load = 50 pf rise and fall matching 90 111.1 % exclude transition from idle output voltage crossover 1.3 2.0 v exclude transition from idle full speed jitter c load = 50 pf driver jitter generated ? 2 + 2 ns next t ransitions ? 1 + 1 ns paired t ransitions load capacitance 50 pf testing slew rate
ADUCM350 data shee t rev. a | page 10 of 40 lcd, charge pump table 18. lcd, charge pump specifications parameter min typ max unit test conditions/comments capacitance reservoir capacitan ce between vlcdvdd and vlcd_gnd 0.47 1 f flying capacitance 2.2 4.7 nf between vlcd fly1 and vlcd fly2 vlcd switching voltage vlcd fly1 ?0.7 vlcd + 0.2 v top of flying capacitor vlcd fly2 0 vccm v bottom of flying capacitor vlcd charge pump switching frequency 32 khz minimum vlcd with respect to vccm_ana and vccm_dig 2.1 v when <2.1 v after 62.5 ms elapses indicates fault condition vlcdvdd vlcdvdd voltage range 2.4 3.65 v 5- bit programmable in steps of 40 mv vlcdvdd pin leakage 3 na to vccm 0.2 na to gnd vlcdvdd start - up time 5 ms vlcdvdd = 0 v to 3.6 v, reservoir = 1 f, flying capacitor = 2.2 nf (m inimum) and 4.7 nf (max imum) vlcdvdd line regulation 0.32 % v_lcd_xx voltage range v_lcd_13 voltage range vlcd 3 ? 10 vlcd 3 + 10 mv v_lcd_23 voltage range 2/3 vlcd ? 13 2/3 vlcd + 13 mv comx pins dc voltage across segment and comx pins 50 mv pin output impedance segment 2000 common 130 system clocks / timers the following tables document the system clock specifications in the ADUCM350 . platform external crystal oscillator table 19. platform external crystal oscillator specifications parameter min typ max unit test conditions/comments low frequency c ext 1 = c ext 2 12 15 18 pf external cap acitor, c1 = c2 (symmetrical load) frequency 32,768 hz high frequency c ext 1 = c ext 2 10 12 15 pf external cap acitor frequency 8 or 16 mhz
data sheet ADUCM350 rev. a | page 11 of 40 o n- chip rc oscillators table 20. on - chip rc oscillators specifications parameter min typ max unit test conditions/comments high frequency rc oscillator frequency 16 mhz accuracy ? 5 + 5 % start - up time 35 s low frequency rc oscillator frequency 32,768 hz accuracy ? 20 + 20 % start -u p time 980 s plls table 21. pll specifications parameter min typ max unit test conditions/comments system pll input frequency 8 16 mhz output frequency 16 32 mhz frequency error 2500 ppm rms jitter 92 ps @ 32 mhz , e xternal xtal usb pll input frequency 8 16 mhz output frequency 16 60 mhz 16 mhz input frequency error 2500 ppm period jitter 68 ps @ 60 mhz , e xternal xtal watchdog , wake - u p, and general - purpose timer s table 22. watchdog, wake - up, and general - purpose timers specifications parameter 1 min typ max unit test conditions/comments watchdog timers timeout period shortest 0.03 ms 32,768 hz clock, p rescaler = 1 longest 8191 s ec 32,768 hz clock, prescaler = 4 096 wake - up timers timeout period shortest 62.5 ns 16 mhz clock, prescaler = 1 longest 136 years 32,768 hz clock, prescaler = 32,768 general - purpose timer 3 timeout period shortest 62.5 ns 16 mhz clock, prescaler = 1 longest 65,535 sec 32,768 hz clock, prescaler = 32,768 timer out put pwm frequency 1 16 mhz 1 guaranteed by design.
ADUCM350 data shee t rev. a | page 12 of 40 power management spe cifications the following tables cover the specifications for the power management section of the ADUCM350 . power supplies tale 2 power supplies specifications parameter min typ max unit test conditions/comments supplies vccm_ana/ vccm_dig 2 3.6 v vccm_x pins connected to the cr 2032 battery , m ain supply for ADUCM350 vccm_ana/ vccm_dig 2.5 3.6 v battery operating range vback 1.62 3.6 v super capacitor pin, back - up mode supply vbus 4.75 5 5.25 v usb 5 v s upply vdd_io 1.8 3.6 v supply for some d igital i/o p ads ; see table 35 , i/o supply column for details vlcdvdd 1.8 3.6 v supply for lcd i / o power supply monitoring tale 2 power supply monitoring specifications parameter 1 min typ max unit test conditions/comments vccm psm voltage detection range 1.7 3.2 v 100 mv step size hysteresis 10 100 mv trip point detection accuracy hysteresis + 70 mv vrtc psm voltage detection range 1.55 1.7 v 100 mv step size hysteresis 25 100 mv trip point detection accuracy hysteresis + 70 mv vback psm voltage detection range 1.7 3.2 v 100 mv step size hysteresis 100 mv trip point detection accuracy hysteresis + 70 mv 1 for details regarding these parameters, see the ug - 587 hardware reference manual . trickle charger table 25. trickle charger specifications parameter min typ max unit test conditions/comments current charge current 0.48 ma l imit s load on button cell at power -up reverse current 1 a voltage forward voltage 40 120 mv where forward current reduces to zero
data sheet ADUCM350 rev. a | page 13 of 40 timing characteristi cs lcd segment/ common timing specifications table 26. lcd segment/common timing specifications 1, 2 framesel[3] framesel[2] framesel[1] framesel[0] static mux 4 mux f lcd (hz) frame rate (hz) f lcd (hz) frame rate (hz) 0 0 0 0 256 128 1024 128 0 0 0 1 204.8 102.4 819.2 102.4 0 0 1 0 170.7 85.3 682.7 85.3 0 0 1 1 146.3 73.1 585.1 73.1 0 1 0 0 128 64 512 64 0 1 0 1 113.8 56.9 455.1 56.9 0 1 1 0 102.4 51.2 409.6 51.2 0 1 1 1 93.1 46.5 372.4 46.5 1 0 0 0 85.3 42.7 341.3 42.7 1 0 0 1 78.8 39.4 315.1 39.4 1 0 1 0 73.1 36.6 292.6 36.6 1 0 1 1 68.3 34.1 273.1 34.1 1 1 0 0 64 32 256 32 1 1 0 1 60.2 30.1 240.9 30.1 1 1 1 0 56.9 28.4 227.6 28.4 1 1 1 1 53.9 26.9 215.6 26.9 1 f lcd = f b clk / ( framesel + 4) . se e the ug - 587 hardware reference manual for details 2 framesel[3], framesel[2], framesel[1], and framesel[0] indicate the bit numbers in the lcd_com register. i 2 c timing capacitive load for each of the i 2 c us line s ( c b ) pf maximum as per i 2 c us specifications i 2 c timing is guaranteed y design and not production tested table 27. i 2 c timing in fast mode (400 khz) parameter description min max unit t l clock low pulse width 1300 ns t h clock high pulse width 600 ns t shd start condition hold time 600 ns t dsu data setup time 100 ns t dhd 1 data hold time 0 ns t rsu setup time for repeated start 600 ns t psu stop condition setup time 600 ns t buf bus - free time between a stop condition and a start condition 1.3 s t r rise time for both clock and data 20 + 0.1 cb 300 ns t f fall time for both clock and data 20 + 0.1 cb 300 ns t sup pulse width of spike suppressed 0 50 ns 1 a device must internally provide a hold t ime of at least 300 ns for the sda signal (with respect to the v inh (minimum ) of the scl signal) to bridge the undefined region of the falling edge of scl. table 28. i 2 c timing in standard mode (100 khz) parameter description min max unit t l clock low pulse width 4.7 s t h clock high pulse width 4.0 ns t shd start condition hold time 4.7 s t dsu data setup time 250 ns t dhd 1 data hold time 0 s t rsu setup time for repeated start 4.0 s
ADUCM350 data sheet rev. a | page 14 of 40 parameter description min max unit t psu stop condition setup time 4.0 s t buf bus-free time between a stop condit ion and a start condition 4.7 s t r rise time for both clock and data 1 s t f fall time for both clock and data 300 ns 1 a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v inh (minimum) of the scl signal) to bridge the undefined region of the falling edge of scl. figure 2. i 2 c-compatible in terface timing sda (i/o) t buf msb lsb ack msb 1 9 8 2 to 7 1 scl (i) ps stop condition start condition s(r) repeated start t sup t r t f t f t r t h t l t sup t dsu t dhd t rsu t dhd t dsu t shd t psu 12073-002
data sheet ADUCM350 rev. a | page 15 of 40 i 2 s timing specifications i 2 s timing is guaranteed by design and not production tested; timing specifications are given for a standard i 2 s data rate of 2.5 mhz; the i 2 s bus is designed to operate up to 25 mhz. table 29. i 2 s timing: master transmitter parameter symbol min typ max unit test conditions/comments 1 i 2 s master transmitter timing sclk period t 360 400 440 ns minimum clock period t tr 360 ns t tr is the minimum allowed clock period for the transmitter, t > t tr clock high period t hc 160 ns minimum > 0.35 t = 140 ns clock low period t lc 160 ns minimum > 0.35 t = 140 ns delay t dtr 300 ns minimum < 0.80 t = 320 ns data hold time t htr 100 ns minimum > 0 ns clock rise time t rc 60 ns minimum > 0.15 t tr = 54 ns (slave mode only) 1 t refers to the typical value listed for the sclk period; the refore, t = 400 ns in this case. table 30. i 2 s timing: slave receiver parameter symbol min typ max unit test conditions/comments 1 i 2 s slave receiver timing sclk period t 360 400 440 ns t tr = 360 ns clock high period t hc 110 ns minimum < 0.35 t = 126 ns clock low period t lc 160 ns minimum < 0.35 t = 126 ns data setup time t sr 300 ns minimum < 0.20 t = 72 ns data hold time t htr 100 ns minimum < 0 ns 1 t refers to the typical value listed for the sclk period; the refore, t = 400 ns in this case. figure 3. i 2 s-compatible interface transmitter timing sclk s d/ws notes 1. sd = serial data, ws = word select, ws = 0: channel 1 (left), ws = 1: channel 2 (right). * t rc is only relevant for transmitters in slave mode. t rc * t htr 0 t lc 0.35t t hc 0.35t v h = 2.0v v l = 0.8v t t dtr 0.8t 12073-003
ADUCM350 data sheet rev. a | page 16 of 40 figure 4. i 2 s-compatible interface receiver timing spi timing spih can be used for high data rate peripherals. table 31. spi master mode timing 1 parameter description min typ max unit t sl sclk low pulse width 2 (spixdiv[5:0] + 1) t uclk ns t sh sclk high pulse width 2 (spixdiv[5:0] + 1) t uclk ns t dav data output valid after sclk edge 0 35.5 ns t dosu data output setup before sclk edge 2 (spidiv + 1) t uclk ns t dsu data input setup time before sclk edge 58.7 ns t dhd data input hold time after sclk edge 16 ns t df data output fall time 12 35.5 ns t dr data output rise time 12 35.5 ns t sr sclk rise time 12 35.5 ns t sf sclk fall time 12 35.5 ns 1 guaranteed by design. 2 t uclk = 62.5 ns. it corresponds to the maximum internal clock frequency before clock dividers. figure 5. spi master mode timing (phase mode = 1) sclk sd and ws t s r 0.2t v h = 2.0v v l =0.8v t htr 0 t lc 0.35t t hc 0.35t t 12073-004 notes 1. sd = seri a l data, ws = word select, ws = 0: channel 1 (left), ws = 1: channel 2 (right). sclk (polarity = 0) cs 1/2 sclk cycle sclk (polarity = 1) mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t sh t cs t sl 3/4 sclk cycle t sfs t sr t sf t dr t df t dav t dsu t dhd 12073-005
data sheet ADUCM350 rev. a | page 17 of 40 figure 6. spi master mode timing (phase mode = 0) table 32. spi slave mode timing parameter description min typ max unit t cs cs to sclk edge 38 ns t sl sclk low pulse width 1 (spixdiv[5:0] + 1) t uclk ns t sh sclk high pulse width 1 62.5 (spidiv[5:0] + 1) t uclk ns t dav data output valid after sclk edge 49.1 ns t dsu data input setup time before sclk edge 20.2 ns t dhd data input hold time after sclk edge 10.1 ns t df data output fall time 12 35.5 ns t dr data output rise time 12 35.5 ns t sr sclk rise time 12 35.5 ns t sf sclk fall time 12 35.5 ns t docs data output valid after cs edge 25 ns t sfs cs high after sclk edge 0 ns 1 t uclk = 62.5 ns. it corresponds to the maximum internal clock frequency before clock dividers. figure 7. spi slave mode timing (phase mode = 1) sclk (polarity = 0) sclk (polarity = 1) mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t sh t sr t sf t dr t df t dav t dosu t dsu t dhd cs 1 sclk cycle t cs t sl 1 sclk cycle t sfs 12073-006 sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso msb bit 6 to bit 1 lsb mosi msb in bit 6 to bit 1 lsb in t dhd t dsu t dav t dr t df t cs 12073-007
ADUCM350 data sheet rev. a | page 18 of 40 figure 8. spi slave mode timing (phase mode = 0) sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso mosi msb in bit 6 to bit 1 lsb in t dhd t dsu msb bit 6 to bit 1 lsb t docs t dav t dr t df t cs 12073-008
data sheet ADUCM350 rev. a | page 19 of 40 absolute maximum ratings t a = 25c, unless otherwise noted. table 33. parameter rating supplies vccm_ana, vccm_dig, vlcdvdd, vdd_io, vback to agnd_x/dgndx ?0.3 v to +3.6 v decoupling dvdd, avdd_rx/tx, vbias, vref, vusb ?0.3 v to +2.0 v digital input/output p0.x, p1.x, p2.x, p3.x, p4.x, boot, resetx ?0.3 v to +3.6 v tracex ?0.3 v to +3.6 v switch matrix (rcal 1, rcal 2, afe x) ?0.3 v to +3.6 v tia (tia_i, tia_o) ?0.3 v to +3.6 v analog inputs (an_x) ?0.3 v to +3.6 v ref_excite ?0.3 v to +1.98 v vlcd fly1, vlcd fly2 ?0.3 v to +3.6 v v_lcd_13, v_lcd_23 ?0.3 v to +3.6 v vbus to dgnd ?0.3 v to +5.25 v usb dm, usb dp to dgnd ?0.3 v to +3.6 v hf_xtalx, lf_xtalx ?0.3 v to +1.98 v analog ground to digital ground agnd ctouch, agnd_rx/tx, agnd_ref to dgnd, dgnd1, dgnd2, dgnd usb ?0.3 v to +0.3 v stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages; assumes use of a jedec 4-layer board. table 34. thermal resistance package type ja unit csp_bga 35 c/w esd caution
ADUCM350 data shee t rev. a | page 20 of 40 pin configuration and function descripti ons figure 9 . bump location (top view looking through device, bumps not to s cale) table 35 . pin function descriptions pin no. mnemonic i/o 1 i/o supply 2 gpio pull - up/down 2 description power and ground p4 vccm_ana s vccm_ana n/a battery connection and analog circuit power. connect vccm_ana to the cr2032 battery . vccm_ana p ower s the analog circuits . this pin is connected to vccm_dig internally. h6 vccm_dig s vccm_dig n/a battery connection and digital circuit power. connect vccm_dig to the cr2032 battery . vccm_dig p ower s the digital circuits . this pin is connected to vccm_ana internally. g2 vbus s vbus n/a 5 v usb supply voltage. m1 vback s vback n/a rtc s upply . connect vback to the super capacitor. h15 vdd_io s vdd_io n/a vdd_io s upply . e1 vusb a vusb n/a regulated usb 3.6 v s upply . r10 vref a n/a n/a 1.8 v reference voltage decoupling capacitor pin. p10 vbias a n/a n/a 1.1 v bias voltage decoupling capacitor pin . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e f g h j k l m n p r tia_o tia_i afe 7 afe 5 afe 3 afe 2 afe 1 rca l 2 rca l 1 an_b an_c vbias vref afe 8 afe 6 afe 4 a vdd_rx/ a vdd_tx vccm_ an a an_ a an_d ref_ excite agnd_rx/ agnd_tx agnd ct ouch p3.7/urx/ t outc/ spi1_cs p3.6/utx/ t outb/ spi1_mosi p3.4/ i2cscl/ spi1_sclk p3.1/ spi0_miso p0.14/ spih_mosi p0.12/ spih_sclk p0.2/ capt_c p0.3/ capt_d dgnd p3.5/ i2csd/ spi1_miso resetx agnd_ref p0.4/ capt_e p0.1/ capt_b p3.0/ spi0_sclk p3.14/ lrclk p3.13/ beepx/ sdat a p3.12/ beep/ bmclk dgnd usb p0.0/ capt_ a p0.5/ capt_f p3. 1 1/s32 p3.10/s31 p3.9/s30 p3.8/s29 p2.15/s28 vccm_ dig p2.7/s20/ t ou ta p2.9/s22 p2.10/s23 p2. 1 1/s24 p2.12/s25 p2.13/s26 p2.14/s27 p2.6/ s19/te p1.15/ s18/d15 p1.14/ s17/d14 p1.13/ s16/d13 p1.12/ s15/d12 p1. 1 1/ s14/d 11 p1.10/ s13/d10 p1.9/s12/ d9 dgnd2/ lcd_gnd p1.3/s6/ d3 p1.4/s7/ d4 p1.5/s8/ d5 p1.6/s9/ d6 p1.7/s10/ d7 p1.8/s 1 1/ d8 p2.3/ com3/ dcx p2.2/ com2/ csx v_lcd_23 p1.2/s5/ d2/din p1.1/s4/ d1/dout p1.0/s3/ d0/sc l p2.5/s2/ eclock- wrx p2.4/s1/ r wx-rdx p2.1/ com1/ resx p2.0/ com0 p2.8/s21 dgnd1 dnc p3.3/ spi0_cs p3.2/ spi0_mosi vdd_io traceclk trace0 trace2 trace3 trace1 trst lf_x t al1 p0. 11 p0.15/ spih_cs tck- swclk/ p0.9 tms- swdio/ p0.8 lf_x t al2 p0.13/ spih_miso tdo-swo/ p0.6/utx p0.10/ t outc p4.2/ t outb p4.1/ i2csd tdi/p0.7/ urx p4.0/ i2csc l vback vbus usb d p vusb usb dm vlcdvdd hf_x t al2 v_lcd_13 hf_x t al1 vlcd f l y2 vlcd f l y1 dvdd boot 12073-009
data sheet ADUCM350 rev. a | page 21 of 40 pin no. mnemonic i/o 1 i/o supply 2 gpio pull - up/down 2 description k1 dvdd a n/a n/a 1.8 v digital regulator decoupling capacitor pin. r4 avdd_rx/ avdd_ tx a avdd tx/rx n/a 1.8 v analog regulator decoupling capacitor pin for receiver ( r x) / transmitter ( t x) c ircuits . k9 agnd_rx / agnd_ tx g n/a n/a rx/tx analog ground. k10 agnd_ref g n/a n/a reference g round . h14 dgnd g n/a n/a digital g round . g6 dgnd1 g n/a n/a digital g round . f7 dgnd2/ lcd_gnd g n/a n/a digital ground/g round for lcd . f6 dgnd usb g n/a n/a usb g round . c onnect dgnd usb to the digital ground plane . afe pins p12 an_a a vccm_ana n/a adc mux input. p13 an_b a vccm_ana n/a adc mux input. r13 an_c a vccm_ana n/a adc mux input. r14 an_d a vccm_ana n/a adc mux input. p5 rcal 1 a vccm_ana n/a terminal a of calibration resistor. c onnect rcal 1 to the switch matrix . r5 rcal 2 a vccm_ana n/a terminal b of calibration resistor. c onnect rcal 2 to the switch matrix . r6 afe 1 a vccm_ana n/a uncommitted afe pin 1 . p6 afe 2 a vccm_ana n/a uncommitted afe pin 2 . r7 afe 3 a vccm_ana n/a uncommitted afe pin 3 . p7 afe 4 a vccm_ana n/a uncommitted afe pin 4 . r8 afe 5 a vccm_ana n/a uncommitted afe pin 5 . p8 afe 6 a vccm_ana n/a uncommitted afe pin 6 . r9 afe 7 a vccm_ana n/a uncommitted afe pin 7 . p9 afe 8 a vccm_ana n/a uncommitted afe pin 8 . p11 tia_i a vccm_ana n/a trans impedance amplifier input . connect the iv resistor to this pin . r11 tia_o a vccm_ana n/a trans impedance amplifier output . connect the iv resistor to this pin . r12 ref_excite a vccm_ana n/a gated precision reference voltage . debug interface j1 tdo -swo/p0.6/utx i/o vccm_dig pull -up jtag serial data output or serial wire trace output / gpio / uart_tx . this is a multifunction pin. j2 tdi/p0.7/urx i/ o vccm_dig pull - u p jtag serial data input / gpio / uart_rx . this is a multifunction pin. h1 tms - swdio/p0.8 i/o vccm_dig pull -up jtag test mode select or serial wire data / gpio . this is a multifunction pin. h2 tck -swclk/p0.9 i/ o vccm_dig pull -d own jtag test clock or serial wire clock / gpio . this is a multifunction pin. r15 trst i vccm n/a trace reset. m15 traceclk o vccm n/a trace clock. m14 trace0 o vccm n/a trace data 0. n15 trace1 o vccm n/a trace data 1. n14 trace2 o vccm n/a trace data 2. p15 trace3 o vccm n/a trace data 3.
ADUCM350 data shee t rev. a | page 22 of 40 pin no. mnemonic i/o 1 i/o supply 2 gpio pull - up/down 2 description spi h r3 p0.12/spih_sclk i/o vccm_dig pull -up gpio / serial port h clock. this is a dual function pin. p2 p0.13/spih_miso i/o vccm_dig pull -up gpio / serial p ort h miso . this is a dual function pin. p3 p0.14/spih_mosi i/o vccm_dig pull -up gpio / serial p ort h mosi . this is a dual function pin. m2 p0.15/spih_cs i/o vccm_dig pull -up gpio / serial p ort h chip select (active low) . this is a dual function pin. other serial ports f14 p3.0/spi0_sclk i/o vdd_io pull -up gpio / spi 0 sclk. this is a dual function pin. g14 p3.1/spi0_miso i/o vdd_io pull - u p gpio / spi 0 miso . this is a dual function pin. f15 p3.2/spi0_mosi i/o vdd_io pull -up gpio / spi 0 mosi . this is a dual function pin. f10 p3.3/spi0_cs i/o vdd_io pull -up gpio /spi 0 chip select (active low) . this is a dual function pin. g10 p3.4/i2cscl/spi1_sclk i/o vdd_io pull -up gpio ( external interrupt 7)/i 2 c c lock / spi 1 sclk . this is a multifunction pin. h10 p3.5/i2csd/spi1_miso i/o vdd_io pull -up gpio /i2c d ata / spi 1 miso . this is a multifunction pin. g15 p3.6/utx/toutb/spi1_mosi i/o vdd_io pull -up gpio / uart tx / timer b output / spi 1 mosi . this is a multifunction pin. j10 p3.7/urx/toutc/spi1_cs i/o vdd_io pull -up gpio / uart rx / timer c output / spi 1 chip select (active low) . this is a multifunction pin. usb f1 usb dm i/o vccm_dig n/a usb data ?. g1 usb dp i/o vccm_dig n/a usb data + . cap touch interface k15 p0.0/capt_a a vccm_dig pull -up gpio (ext ernal in terrupt 1) /capt ouch a . this is a dual function pin. j15 p0.1/capt_b a vccm_dig pull -up gpio ( external interrupt 2) /capt ouch b. this is a dual function pin. l15 p0.2/capt_c a vccm_dig pull -up gpio ( external interrupt 3) /capt ouch c . this is a dual function pin. k14 p0.3/capt_d a vccm_dig pull - u p gpio ( external interrupt 4) /capt ouch d . this is a dual function pin. j14 p0.4/capt_e a vccm_dig pull -up gpio ( external interrupt 5) /capt ouch e . this is a dual function pin. l14 p0.5/capt_f a vccm_dig pull -up gpio ( external interrupt 6) /capt ouch f . this is a dual function pin. p14 agnd ctouch g n/a n/a capacitance to digital converter ac s hield . system clocks p1 lf_xtal1 a rtc_ vback n/a 32 khz xtal p in. n1 lf_xtal2 a rtc_vback n/a 32 khz xtal pin. d1 hf_xtal1 a dvdd n/a 16 mhz xtal p in . c1 hf_xtal2 a dvdd n/a 16 mhz xtal p in . display e2 vlcd fly1 a vlcd vdd n/a lcd f lying c apacitor top plate. f2 vlcd fly2 a vlcd vdd n/a lcd flying capacitor bottom plate. d2 vlcdvdd s n/a n/a full - scale lcd voltage output or vlcd supply. c2 v_lcd_13 a vlcd vdd n/a one - third (1/3) lcd voltage. leave this pin as no connect. b1 v_lcd_23 a vlcd vdd n/a two - thirds (2/3) lcd voltage. leave this pin as no connect.
data sheet ADUCM350 rev. a | page 23 of 40 pin no. mnemonic i/o 1 i/o supply 2 gpio pull - up/down 2 description b2 p2.0/com0 i/o vlcd vdd pull -up gpio/common output 0 for lcd back plane (com 0). this is a dual function pin. a2 p2.1/com1/resx i/o vlcd vdd pull -up gpio/com 1/parallel display interface (pdi) reset. this is a multifunction pin. b3 p2.2/com2/csx i/o vlcd vdd pull -up gpio/com 2/pdi chip select. this is a multifunction pin. a3 p2.3/com3/dcx i/o vlcd vdd pull -up gpio/com 3/pdi data select. this is a multifunction pin. b4 p2.4/s1/rwx- rdx i/o vlcd vdd pull -up gpio/segment driver 1 (seg 1)/pdi r/wx or rdx. this is a multifunction pin. a4 p2.5/s2/eclock- wrx i/o vlcd vdd pull -up gpio/seg 2/pdi e clock output (motorola bus mode) or pd write select (intel? bus mode). this is a multifunction pin. a5 p1.0/s3/d0/scl i/o vlcd vdd pull - down gpio/seg 3/pdi d0/pdi serial port clock. this is a multifunction pin. b5 p1.1/s4/d1/dout i/o vlcd vdd pull - down gpio/seg 4/pdi d1/pdi serial port data output. this is a multifunction pin. a6 p1.2/s5/d2/din i/o vlcd vdd pull - down gpio/seg 5/pdi d2/pdi serial port data input. this is a multifunction pin. b6 p1.3/s6/d3 i/o vlcd vdd pull - down gpio/seg 6/pdi d3. this is a multifunction pin. a7 p1.4/s7/d4 i/o vlcd vdd pull - down gpio/seg 7/pdi d4. this is a multifunction pin. b7 p1.5/s8/d5 i/o vlcd vdd pull - down gpio/seg 8/pdi d5. this is a multifunction pin. a8 p1.6/s9/d6 i/o vlcd vdd pull - down gpio/seg 9/pdi d6. this is a multifunction pin. b8 p1.7/s10/d7 i/o vlcd vdd pull - down gpio/seg 10/pdi d7/system clock output. this is a multifunction pin. a9 p1.8/s11/d8 i/o vlcd vdd pull - down gpio/seg 11/pdi d8. this is a multifunction pin. b9 p1.9/s12/d9 i/o vlcd vdd pull - down gpio/seg 12/ pdi d9. this is a multifunction pin. a10 p1.10/s13/d10 i/o vlcd vdd pull - down gpio/seg 13/pdi d10. this is a multifunction pin. b10 p1.11/s14/d11 i/o vlcd vdd pull - down gpio/seg 14/pdi d11. this is a multifunction pin. a11 p1.12/s15/d12 i/o vlcd vdd pull - down gpio/seg 15/pdi d12. this is a multifunction pin. b11 p1.13/s16/d13 i/o vlcd vdd pull - down gpio/seg 16/pdi d13. this is a multifunction pin. a12 p1.14/s17/d14 i/o vlcd vdd pull - down gpio/seg 17/pdi d14. this is a multifunction pin. b12 p1.15/s18/d15 i/o vlcd vdd pull - down gpio/seg 18/pdi d15. this is a multifunction pin. d15 p2.6/s19/te i/o vlcd vdd pull - down gpio/seg 19/te. this is a multifunction pin. c15 p2.7/s20/touta i/o vlcd vdd pull - down gpio/seg 20 /timer a output. this is a multi - function pin. b15 p2.8/s21 i/o vlcd vdd pull - down gpio/seg 21. this is a dual function pin. a14 p2.9/s22 i/o vlcd vdd pull - down gpio/seg 22. this is a dual function pin. a13 p2.10/s23 i/o vlcd vdd pull - down gpio/seg 23. this is a dual function pin. b13 p2.11/s24 i/o vlcd vdd pull - down gpio/seg 24. this is a dual function pin. b14 p2.12/s25 i/o vlcd vdd pull -up gpio/seg 25. this is a dual function pin. d14 p2.13/s26 i/o vlcd vdd pull - up gpio/seg 26. this is a dual function pin. e15 p2.14/s27 i/o vlcd vdd pull -up gpio/seg 27. this is a dual function pin. a15 p2.15/s28 i/o vlcd vdd pull -up gpio/seg 28. this is a dual function pin. f8 p3.8/s29 i/o vlcd vdd pull -up gpio/seg 29. this is a dual function pin. f9 p3.9/s30 i/o vlcd vdd pull -up gpio/seg 30. this is a dual function pin. c14 p3.10/s31 i/o vlcd vdd pull -up gpio/seg 31. this is a dual function pin. e14 p3.11/s32 i/o vlcd vdd pull - up gpio/seg 32. this is a dual function pin.
ADUCM350 data shee t rev. a | page 24 of 40 pin no. mnemonic i/o 1 i/o supply 2 gpio pull - up/down 2 description miscellaneous digital input/output k8 resetx i vccm_dig pull -up reset pin (active low). l1 p4.0/i2cscl i/o vccm_dig pull -up gpio (external interrupt 0)/i 2 c clock. this is a dual function pin. l2 p4.1/i2csd i/o vccm_dig pull -up gpio/i 2 c data. this is a dual function pin. r1 p4.2/toutb i/o vccm_dig pull - up gpio/timer b output. this is a dual function pin. r2 p0.10/toutc i/o vccm_dig pull -up gpio (external interrupt 8)/timer c output. this is a dual function pin. k2 p0.11 i/o vccm_dig pull -up gpio (external clock input pin). n2 boot i vccm_dig pull - down the device enters serial download mode if this pin is held high during, and for a short time after, a reset. it executes user code after any reset event or if the pin is low. a1 dnc n/a n/a do not connect. leave this pin floating. audio k6 p3.12/beep/bmclk i/o vccm_dig pull - down gpio/beeper output positive/i 2 s bit clock. this is a multifunction pin. k7 p3.13/beepx/sdata i/o vccm_dig pull - down gpio/beeper output negative/i 2 s serial data output. this is a multifunction pin. j6 p3.14/lrclk i/o vccm_dig pull - down gpio/i 2 s frame clock. this is a dual function pin. 1 s is s upply, a is a nalog input, i is d igital input, o is d igital output, i/o is digital input/output, and g is g round . 2 n/a means not applicable.
data sheet ADUCM350 rev. a | page 25 of 40 typical performance characteristics figure 10 . aldo line regulation figure 11 . aldo load regulation figure 12 . vref line regulation figure 13 . vref load regulation figure 14 . ref_excite load regulation figure 15 . vbias line regulation 1.7980 1.7985 1.7990 1.7995 1.8000 1.8005 1.8010 2.50 2.75 3.00 3.25 3.50 aldo vo lt age (v) vccm (v) 10m a load 12073-010 1.790 1.795 1.800 1.805 1.810 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 aldo vo lt age (v) aldo current (a) 12073-0 1 1 1.80050 1.80055 1.80060 1.80065 1.80070 1.80075 1.80080 1.80085 1.80090 1.80095 1.80100 2.5 2.7 2.9 3.1 3.3 3.5 vref (v) vccm (v) 300 a load on v ref 12073-012 1.8000 1.8001 1.8002 1.8003 1.8004 1.8005 1.8006 1.8007 1.8008 1.8009 1.8010 ?0.0003 ?0.0002 ?0.0001 0 vref vo lt age (v) load current (a) vccm = 3.6v vccm = 2.5v 12073-013 1.792 1.794 1.796 1.798 1.800 1.802 1.804 ?0.0003 ?0.0002 ?0.0001 0 ref_excite vo lt age (v) ref_excite load current (a) 12073-014 1.09990 1.09992 1.09994 1.09996 1.09998 1.10000 1.10002 1.10004 2.5 2.7 2.9 3.1 3.3 3.5 vbias (v) vccm (v) 12073-015
ADUCM350 data sheet rev. a | page 26 of 40 figure 16. adc tia_o inl (16-bit) vs. code (150 a) figure 17. adc adc tia_o dnl (16-bit) vs. code figure 18. adc adc tia_o inl (16-bit) vs. code (temperature) figure 19. adc tia_o dnl (16- bit) vs. code (temperature) figure 20. adc an_a inl (16-bit) vs. code figure 21. adc an_a dnl (16-bit) vs. code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 10200 15200 20200 25200 30200 35200 40200 45200 50200 tia_o inl (lsb) c o d e 12073-016 v c c m = 3 . 6 v v c c m = 3 . 0 v v c c m = 2 . 4 v v c c m ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 tia_o dnl (lsb) 10200 15200 20200 25200 30200 35200 40200 45200 50200 c o d e 12073-017 v c c m = 3 . 6 v v c c m = 3 . 0 v v c c m = 2 . 4 v v c c m ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 10000 15000 20000 25000 30000 35000 40000 45000 50000 tia_o inl (lsb) code 50c 25c 0c vccm = 3.0 v 12073-018 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 10000 15000 20000 25000 30000 35000 40000 45000 50000 tia_o dnl (lsb) code 50c 25c 0c vccm = 3.0 v 12073-019 17500 22500 27500 32500 37500 42500 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 an _ a inl (lsb) code 12073-020 vccm = 3.6v vccm = 3.0v vccm = 2.4v vccm ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 17500 22500 27500 32500 37500 42500 an _ a dnl ( lsb ) code 12073-021 vccm = 3.6v vccm = 3.0v vccm = 2.4v vccm
data sheet ADUCM350 rev. a | page 27 of 40 figure 22 . adc a n_ a inl (16 - bit) vs . c ode (temperature) figure 23 . adc a n_a dnl (16 - bit) vs . code ( temperature) figure 24 . receive channel antia lias filter roll - off figure 25 . dac inl (12 - bit) vs. code figure 26 . dac dnl (12 - bit) vs. code figure 27 . noise spectral density 17510 22510 27510 32510 37510 42510 47510 an _a in l (lsb) code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 50c 25c 0c v ccm = 3.0v 12073-022 an _a dn l (lsb) 17510 22510 27510 32510 37510 42510 47510 code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 50c 25c 0c vccm = 3.0v 12073-023 ?18 ?15 ?12 ?9 ?6 ?3 0 1k 10k 100k amplitude (db) frequenc y (hz) 12073-024 3.6v 3.0v 2.4v ?0.6 ?1.0 ?0.8 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 500 1000 1500 2000 code 2500 3000 3500 4000 dac in l (lsb) measured across rcal a tten off com p off dac code 0x200 t o 0xe00 2.5v 3.0v 3.6v 12073-025 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 0 500 1000 1500 2000 2500 3000 3500 4000 dac dn l (lsb) code measured across rcal a tten off com p off dac code 0x200 t o 0xe00 2.5v 3.0v 3.6v 12073-026 0.01 0.1 1 10 100 1 10 100 1k 10k 100k (v/hz) dac code = 0x800 (midscale) vccm = 3.3v measured a t rca l dac_ a tten_en = 0 dac_ a tten_en = 1 frequenc y (hz) 12073-027
ADUCM350 data sheet rev. a | page 28 of 40 figure 28. settling time of the dac at rcal figure 29. impedance measurement magnitude accuracy figure 30. impedance measurement phase accuracy figure 31. impedance measurement magnitude precision figure 32. impedance measurement phase precision figure 33. captouch linearity 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?15 ?10 ?5 0 5 10 15 20 25 30 vol t age a t rc a l (v) time (s) 0xc00 to 0x400 0x400 to 0xc00 12073-028 0 10 20 30 40 50 60 70 80 90 190.94 191.04 191.13 191.23 1 9 1 . 3 2 191.42 number of units impedance magnitude ( ? ) z = 127 ? + 56nf sine amplitude = 9mv rms dac_atten_en = 1 r tia = 7.5k ? 12073-029 1000 ADUCM350 devices measured 0 10 20 30 40 50 60 70 80 90 100 ?48.66 ?48.63 ?48.59 ?48.55 ?48.52 ?48.48 number of units impedance phase () z = 127 ? + 56nf sine amplitude = 9mv rms dac_atten_en = 1 r tia = 7.5k ? 12073-030 1000 ADUCM350 devices measured 0 50 100 150 200 250 300 350 400 450 500 181.5 182.2 183.0 183.7 184.4 185.2 number of units impedance magnitude ( ? ) 12073-032 1000 measurements on 1 ADUCM350 device z = 127 ? + 56nf sine amplitude = 9mv rms dac_atten_en = 1 r tia = 7.5k ? 0 50 100 150 200 250 300 350 400 450 500 40.08 40.28 40.48 40.68 40.88 41.08 mumber of units impedance phase ( ) z = 127 ? + 56nf sine amplitude = 9mv rms dac_atten_en = 1 r tia = 7.5k ? 12073-031 1000 measurements on 1 ADUCM350 device 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 cdc codes input capacitance (pf) 4.662pf_g1 6.993pf_g1 9.324pf_g1 2.331pf_g2 4.662pf_g2 6.993pf_g2 9.324pf_g2 2.331pf_g4 4.662pf_g4 6.993pf_g4 9.324pf_g4 capdac compensated at 50pf autozero = 2s hold time = 2s ph13 = 2s ph23 = 4s 12073-033
data sheet ADUCM350 rev. a | page 29 of 40 figure 34 . captouch snr figure 35 . gpio v ol vs. i ol figure 36 . gpio v oh vs. i oh ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 10 20 30 40 50 60 70 80 amplitude (db) frequenc y (khz) 1khz t one 12073-034 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 v ol (v) i ol (a) gpio p1.1 high drive gpio p1.1 low drive 12073-035 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ?0.016 ?0.014 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 v oh (v) i oh (a) gpio p1.1 high drive gpio p1.1 low drive 12073-036
ADUCM350 data shee t rev. a | page 30 of 40 a nalog f ront e nd figure 37 . afe system block diagram for full details on the ADUCM350 , refer to the ug - 587 hardware reference manual . the ADUCM350 is a high accuracy , configurable , afe with a lo w power, peripheral rich, micro controller subsystem. excitation stage the excitation/ transmit stage consists of a 12 - b it dac with an excitation buffer and an instrumentation amplifier in a feedback path to the dac, which forces an accurate voltage across the impedance to be measure d, thereby removing parasitic s from t he measurement system. all measurements are referenced to a precision external resistor, which is used in the internal calibration loop to ensure no dc bias across an unknown impedance. a large range of impedances can be measured , depending on the applicat ion. users can optimize the calibration resistor ( rcal ) , ac amplitude of the e xcitation waveform , and the current - to - voltage ( i v ) resistor to tailor fit the system to the application demands. impedances can be measured from 80 hz to ~ 75 k hz. the switch matrix offers the user full configurability with 34 user selectable switches. the current carrying switches on both excitation buffer output and the transimpedance input are opti - mally siz e d for current loads. the switch matrix allows the device to measure and store offset and gain results. the ADUCM350 can self calibrate rx o ffset and g ain, tx o ffset and g ain , and switch leakage. this off loads the requirement for an extensive facto ry calibration routine and removes temperature and ag ing induced errors from measurements. rca l 1 afe 1 afe 2 afe 3 afe 4 afe 5 afe 6 afe 7 afe 8 switch ma trix exci ta tion amplifier example configur a tion d p n t rca l r z x y rca l 2 a tten 1 or 40 tem p sens vbias tia_i r ti a tia_o an_ a an_b an_c an_d vccm dvdd a vdd lp rcf 50khz aaf 55khz gain 1 or 1.5 adc mux 12-bit dac gain and offset ca l vrefdac 326.53ksps 160ksps 16-bit adc gain and offset ca l dft n = 2048 (12.8ms) hann window vre f adc singled ended inputs differentia l inputs dac code (arbitra r y) 178 re im sinc2hf sinc2lf 50hz/60hz rejection sine gener a tion trapezoid gener a tion 900sps 900sps 12073-037
data sheet ADUCM350 rev. a | page 31 of 40 figure 38. switch matrix d2 d3 d4 d5 d6 d7 d8 pr1 p2 p3 p4 p5 p6 p7 p8 n1 n2 n3 n4 n5 n6 n7 nr2 t1 t2 t3 t4 t5 t6 t7 tr2 rcal 1 rcal 2 a fe 1 a fe 2 a fe 3 a fe 4 a fe 5 a fe 6 a fe 7 a fe 8 tia_i tia_o 6 r tia excitation excitation amplifier tia t n ivs dr1 vbias d p pl nl 12073-038
ADUCM350 data shee t rev. a | page 32 of 40 measurement stage the afe consists of a multiplexed input , 160 k sps , 16- b it adc with four dedicated voltage measurement channels and up to eight multiplexed current measurement c hannels using the on - chip trans impedance amplifier. the multiplexed channels are filtered and differentially buffered prior to data conv ersion. the adc data can be interrogated using three methods. ? by r aw d ata at 160 k sps . ? at the output of a 50 hz/ 60 hz filter at 900 sps. ? through a d iscrete fourier transform (dft) engine . the power line filter is optimized for fast settling , just 36.6 ms settling. data at 900 sps can be further decimated by the user without requiring additional filtering. figure 39 . power line rejection modeling the dft engine performs a 2048 - point single frequency discrete fourier transform. it takes the 16 - bit adc output and converts it to complex impedance with real and imaginary components. as the adc samples at 160 k sps, this allows for a 79.5 hz signal energy bandwidth, which gives excellent rejection of interferers. figure 40 . frequency response , 2048 - point dft at 20 k hz figure 41 . rx stage magnitude (db) 0 ?20 ?40 ?60 ?80 ?100 0 100 200 300 400 500 frequenc y (hz) notches architected a t 50hz and 60hz t o reject power line interference frequenc y (hz) 600 700 800 900 0 500 1000 1500 2000 2500 3000 3500 4000 0 ?20 ?40 ?60 ?80 magnitude (db) ?100 12073-040 frequenc y (hz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100 50 0 ?50 ?100 ?150 magnitude (db) ?200 12073-041 r ti a c ti a tia_i tia_o vbias an_ a an_b an_c an_d dvdd/2 vccm vbias adc vref = 1.8v + ? + ? + + ? ? + ? + ? + ? a vdd/2 temper a ture sensor antialias fi l tering precision reference v ref 12073-039
data sheet ADUCM350 rev. a | page 33 of 40 afe control figure 42 . afe control the afe can be controlled by the arm cortex - m3 via mmrs. all blocks within the afe are fully controllable and observable using the mmr registers. access t he mmrs through a n ahb bus or indirectly through a programmabl e sequencer. there are two dedicated dma channels to remove burden from the arm cortex - m3 to manage data and control fifos. the sequencer handles low level afe operations and allows the afe to perform its functions independently . it performs cycle accurate precision afe measurements asynchronously of the core. the sequencer allows the user to create parameterized wave - forms using the waveform generator block. the waveforms c an be trapezoids or sinusoids. arbitrary waveforms are possible using the afe seque ncer and dma transfers. figure 43 . waveform generation cap touch features the ADUCM350 incorporates a cap acitive touch subsystem that interfaces with up to six capacitive touch channels in self c apacitance mode and incorporates high performance capacitance sensing circuitry without external components. the sensor input configuration is very flexible and uses several techniques to ensure that there are no false touches (that is, no registering touches caused by a changing environment) on the external sensors. to minimize noise pickup from the system, the ADUCM350 captouch core includes several algori thms , such as median and averaging filtering measurements, as well as configurable excitation frequency and duty cycle. the subsystem includes a self timer and touch - and - release routines to optimize the power consumption and reduce the computing workload i n the arm cortex - m3. figure 44 . cap touch external interface analog blocks 50hz/60hz fi l ter sequencer command fifo ds p acceler a t ors dft w a veform gener a t or dat a fifo (t o m3) interrupt gener a tion mmr afe arm cortex-m3 system bus 12073-042 sine generation trapezoid generation dac code (dc) dac 12073-043 cap t ouch pcb bu_onoff ca p acitive t ouch bu_left bu_right bu_u p bu_down bu_enter agnd_tx 12073-044
ADUCM350 data shee t rev. a | page 34 of 40 micro subsystem memories the memory offering s for the ADUCM350 are as follows : ? 384 kb f lash. ? 16 kb of f lash c onfigured for eeprom emulation. ? 2 kb user information. ? 32 kb sram . ? 2 kb dedicated sram for usb endpoint. flash the ADUCM350 includes 384 kb of embedded flash me mor y, accessed using the flash controller. the flash controller is con - nected to the bus matrix as a slave device for core and dma access, as well as the 32 - bit a h b for mmr access. the f lash controller supports 384 kb of user space and 2 kb of information space. read and write to f lash are executed via ahb only. the 384 kb flash memory comprises one 256 kb f lash array and one 128 kb f lash array. the 256 kb flash memory array and 128 kb f lash array are controlled by two separate f lash controllers with separa te register controls. with respect to f lash integrity, the device supports ? automatic signature check of information space at reset ? user signature for application code ? parity checking on a per access basis ? 20,000 cycle endurance with 20 ms erase and 20 s program ? 100- year data retention at room temperature general - purpose flash the device contains 16 kb of embedded flash memory for general purpose , such as eeprom emulation. sram there is 32 kb of sram on chip of which 16 kb is retained during hibe rnate mode and an optional 16 kb can be retain ed during h ibernate for reduced leakage current. debug capability the ADUCM350 s upports two types of debug host interface : 4 - wire jtag debug (jtag ) interface and a serial 2 - wire debug (swd) interface. the ADUCM350 incorporates the complete embedded trace of the a rm cortex - m3 features to maximize code analysis, system profiling, and debu gging capabilities. programmable gpios the ADUCM350 has 66 gpio pins , m ost of which have multiple, configurable functions defined by user code. they can be configured as an input/output and ha ve programmable pull - up or pull - down resistors. all i/o pins are functional over the full supply range (vbat = 1.8 v to 3.6 v). in power saving mode, gpio pins retain state ; t hey tri sta t e on reset to prevent any bus irritation. gpios of note are as follows : ? 32 pins multiplex ed with lcd segment common pins ? six pins multiplexed with cap touch ? nine pins on a dedicated vddio for eas e of interfacing to peripherals timers general - purpose timers ADUCM350 has three identical general - purpose timers, each with a 16 - bit count - up/count - down counter. the count - up/count - down counter can be clocked from one of four user selectable clock sources. any selected clock source can be scaled dow n using a prescaler of 16, 256 , or 32,768. watch dog timer (wdt) the watchdog timer is a 16 - bit count - down timer with a program - mable prescaler. the prescaler source is selectable and can be scaled by a factor of 1, 16, 256, or 4096. the watchdog timer is clocked either by the 32 khz crystal oscillator (lfxtal) or by the 32 khz on - chip oscillator (lfosc).the watchdog timer (wdt) is used to recover from an illegal software state. after the wut is enabled by user code, it requires periodic servicing to preven t it from forcing a reset or interrupt of the processor. a wdt timeout can generate a reset or an interrupt. wake - up timer the wake - up timer (wut) consists of a 32 - bit counter clocked from the 32 khz external crystal (lfxtal), 32 khz internal oscillator ( lfosc), or peripheral clock (pclk). the selected clock source can be scaled usb the usb port on the ADUCM350 is a usb 2.0 full speed com - pliant port. the module consists of the usb controlle r, usb phy, usb ram , and a 2 - channel dma. an integrated regulator powered by vbus supplies the usb phy. a dedicated pll with 60 mhz clock capability is available for clock generation. the usb supports bulk, isochronous, interrupt , and control modes. it has seven hardware endpoint and a dedicated 2 - channel dma. it supports s uspend and w akeup. the controller hardware is supplemented by a complete set of usb device class drivers to provide complete usb functionality using a defined micrium stack . the usb s tack has a requirement for an rtos to be on the system. analog devices, inc. , has developed its system using the micrium c/os - ii.
data sheet ADUCM350 rev. a | page 35 of 40 power management and clocking power modes the pmu provides control of the ADUCM350 power modes and allows the arm cortex - m3 to control the clocks and power gating to reduce the dynamic power and hibernate power. there are four power modes available ; each mode provides an additional low power benefit with a corresponding reduction in functionality. ? active m ode a ll peripherals can be enabled. active power is managed by optimized clock management. ? core s leep the c ore is clock gated but the re mainder of the system is active. no instructions can be executed in this mode, but dma transfers can continue between peripherals and memory. ? system s leep in system sleep , m ost peripherals are clock gated and are no longer user programmable ; the i nterrupt controller remains active and the nvic processes wake - up events for a limited number of sources. ? hibernate m ode s ome limited state retention, limited number of wake - up interrupts , and the rtc is active. the device also has a back up mode that supplies minimum power t o th e rtc and associated circuitry from a super capacitor . the rtc can run for >12 hours with an 80 mf cap acitor . power management the ADUCM350 has an integrated power management system to opt imize performance and extend battery life of the device. see the ug - 587 hardware reference manual for additional details. the power management system c onsists of ? integrated a nalog and d igital ldos regulated to 1.8 v. ? hibernate mode from 2.0 v to 3.6 v . ? high p erformance afe measurement from 2.5 v to 3.6 v. ? integrated p ower s witches for low standby current in hibernate mode . ? integrated smart diode trickle charger for a super capacitor for use in backup mode. ? dedicated vd dio voltage via nine gpio pins for peripheral interoperability. ? dedicated regulator for usb transceiver and bus supplied from the vusb pin . ? dedicated s upervisory circuits for fail safe operation , including power supply monitors of dvdd during f lash read/writes, psm of v ccm to monitor supply during afe measurements , and psm on the lfxtal block to monitor the clock source for rtc. clocking two on - chip oscillators and driver circuitry for two external crystals are available on the ADUCM350 : lfosc is a 32 khz internal oscillator, hfosc is a 16 mhz internal oscillator, and lfxtal is a 32 khz external crystal oscillator, and hfxtal is a 16 mhz external crystal oscillator. th e ADUCM350 supports either 8 mhz or 16 mhz resonant circuits. the hf rc oscillator has an accuracy of 5%. a low jitter clock source is used for accurate afe measurements. the usb has a freque ncy accuracy requirement of 200 ppm. the usb control logic must be clocked at >30 mhz. a usbphyclk for clocking the usb phy is also available and must use a 60 mhz clock. the low frequency clocking is optimized for ultralow power applications. the rtc req uires that the 32.768 khz xtal be activated to run for 12 hours off a fully charged 0.08 f super capacitor. real time clock the rtc contains a low power crystal oscillation circuit that operates in conjunction with a 32,768 hz external crystal. it achieves 25 ppm performance in keeping time at 25c when used with a 10 ppm crystal class load capacitors. features of the rtc include ? a 32 - bit count register of the time in seconds from a known reference point. ? a prescaler that divides down the 32,768 hz crysta l input to 1 hz to advance the seconds count. ? rtc alarm and interrupt flags. ? digital trim capability to allow a positive or negative adjustment to the rtc count at fixed intervals. display options lcd segment display driver and controller the ADUCM350 contains an on - chip lcd controller capable of directly driving an lcd panel. for lcd functionality, 36 pins are available on the device. the lcd controller supports d riving up to 128 segments , as well as s electable multiplex option. the s tatic option consists of one b ackplane 32 frontplanes and the 4 mux option consists of four backplanes 32 frontplanes. the lcd controller also supports lcd waveform voltages that are generated using internal charge pump circuitry and support levels from 2.4 v up to 3.6 v lcds, programmable frame rates, interrupt generation at the frame boundary (for updating lcd data), and the lcd frame clock (generated by using the on - board 32 khz crystal). lcd display contro ller options the lcd controller also has the ability to drive external lcd display modules. it has 25 pins for the display interface, which support data transfers of up to 16 bits. display controller supports type a, type b , and type c of the mipi dbi specification version 2.0 . specifically, both fixed - e mode and clocked - e mode options of the type a interface are s upported, as well as all bus width options (8 - /9 - /16 - bit da t a) for
ADUCM350 data shee t rev. a | page 36 of 40 type a and type b , and 9 - bit (option 1) and 8 - bit (option 3 ) serial interface s for type c . by using the display controller, the d epth on various interfaces is as follows: ? 8 - bit interface is 8 , 12 , or 16 bits per pixel (not 18 or 24) . ? 9 - bit interface is 18 bits per pixel (not 8 , 12, 16 , or 24) . ? 16- bit interface is 8 , 12 , or 16 bits per pixel (not 18 or 24). audio options the ADUCM350 has an integrated audio driver for b eeper and an integrated i 2 s port. beeper the beeper driver module in the ADUCM350 generates a differential square wave of programmable frequency. it drive s an external piezoelectric sound component whose two terminals connect to the differential square wave output. the beeper driver consists of a module that can deliver frequencies from 8 khz to ~0.25 khz. it operates on a fixed independent 32 khz (32 , 768 hz) clock source that is unaffected by changes in system clocks. a timer allows for programmable tone durations from 4 ms to 1.02 s ec in 4 ms increments. single - tone (pulse) and multitone (sequence) modes provide versatile playback options. in sequence mode, the beeper can be programmed to play any number of tone pairs from 1 to 254 ( 2 to 508 tones) or be programmed to play fore ver (until stopped by the user). interrupts are available to indicate the start or end of any beep, the end of a sequence, or that the sequence is nearing completion. i 2 s the device supp orts i 2 s . the purpose of the i 2 s port is to provide audio data to an amplifier, which drive s a small speaker. the i 2 s features available on the ADUCM350 include the following: ? data samples of up to 24 bits. ? frame clocks from 8 khz to 192 khz. ? master/slave mode. ? 8 - deep tx fifos. ? dma mode with address auto increment. ? interrupt mode. ? downsampling transfers.
data sheet ADUCM350 rev. a | page 37 of 40 development support documentation the ADUCM350 hardware reference manual details the functionality of each block on the ADUCM350 . it includes power management, clocking, memories, peripherals, and the afe. hardware the eval-ADUCM350ebz evaluation kit is available to prototype a users sensor configuration with the ADUCM350 . a selection of daughter cards are available to interrogate peripheral performance, including captouch, pdi, lcd segment, beeper, and i 2 s. software the eval-ADUCM350ebz includes a complete development and debug environment for the ADUCM350 . the software development kit (sdk) for the ADUCM350 uses the iar embedded workbench for arm as its development environment. the sdk consists of full working afe examples of power-up sequences, calibration sequences, and measurement routines. these afe example routines are documented in the ug-587 hardware reference manual with supporting timing diagrams. the sdk also includes operating system (os) aware drivers and example code for all the peripherals on the device, including spi, i 2 c, captouch, pdi, and so forth. also available in the support package is the ADUCM350 afe development gui that operates from the national instruments labview? environment. this gui allows the user to rapidly prototype different sensors with the ADUCM350 afe to evaluate its high precision performance.
ADUCM350 data sheet rev. a | page 38 of 40 packaging and ordering information outline dimensions figure 45. 120-ball chip scale package ball grid array [csp_bga] (bc-120-3) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADUCM350bbcz ?40c to +85c 120-ball chip scale package ball grid array [csp_bga] bc-120-3 ADUCM350bbcz-rl ?40c to +85c 120-ball chip scale package ball grid array [csp_bga] bc-120-3 1 z = rohs compliant part. * compliant to jedec standards mo-275-ccce-1 with exception to package height. 04-02-2013-a 0.35 0.30 0.25 1.08 1.01 0.94 0.50 0.50 ref a b c d e f g 9 10 8 11 12 13 14 15 7 5 642 31 bottom view 7.00 bsc sq h j k l m detail a top view detail a coplanarity 0.08 ball diameter seating plane a1 ball c orne r a1 ball corner 8.10 8.00 sq 7.90 0.22 nom 0.17 min * 1.35 1.23 1.14 n p r
data sheet ADUCM350 rev. a | page 39 of 40 notes
ADUCM350 data shee t rev. a | page 40 of 40 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12073 - 0- 5/14(a) www.analog.com/ ADUCM350

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